What is PrimeTime VLSI?
PrimeTime is a Static Timing Analysis (STA) tool from Synopsys. This is a simple description to use PrimeTime for VLSI class project. In Project #6, you will learn to find critical path using PrimeTime from your synthesized Verilog code.
What is Prime Time tool?
PrimeTime is a stand-alone static timing analysis tool, which is based on the universally adopted EDA tool language, Tcl. A brief section is included on the Tcl language in context of PrimeTime, to facilitate the designer in writing PrimeTime scripts and building upon them to produce complex scripts.
How do I invoke PrimeTime?
PT may be invoked in the command-line mode using the command pt_shell or in the GUI mode through the command primetime.
What are the inputs to PrimeTime?
PrimeTime needs four types of files before you can run it:
- Netlist file: Verilog, VHDL, EDIF.
- Delay file: SPEF(standard parasitic format, it’s from STARRC or place&route tool), SPF, SDF(standard delay format)
- Library file: DB ( From library vendors)
What is static timing analysis in VLSI?
Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations under worst-case conditions. It considers the worst possible delay through each logic element, but not the logical operation of the circuit.
What is scenario in VLSI?
In ICCompiler, we create `scenarios` to specify the different corners and modes the design should operate on. In a `scenario`, you can have constraints which determine the mode of operation, and different libraries(or opertaing conditions) which determine the corners.
Why is it called static timing analysis?
In static timing analysis, the word static alludes to the fact that this timing analysis is carried out in an input-independent manner. It locates the worst-case delay of the circuit over all possible input combinations. There are huge numbers of logic paths inside a chip of complex design.
Why do we use static timing analysis?
The main goal of static timing analysis is to verify that despite these possible variations, all signals will arrive neither too early nor too late, and hence proper circuit operation can be assured. Since STA is capable of verifying every path, it can detect other problems like glitches, slow paths and clock skew.
What is Multi-Mode Multi-corner?
Multi-mode multi-corner (MMMC) analysis refers to performing STA across multiple operating modes, PVT corners and parasitic interconnect corners at the same time.
Why is it important to use multi scenario analysis?
This allows users to reduce the hardware resources and turnaround time for multi-scenario analysis, while maintaining signoff quality timing correlation. Distributed Multi-Scenario Analysis (DMSA) and Interactive Multi-Scenario Analysis (IMSA) allow users to efficiently setup and debug multi-scenario runs.
Which is the best definition of primetime DMSA?
Primetime provides an efficient way to analyze timing at different corners and different operating modes. MMMC (multi-mode multi corner) refers to performing timing analysis at various modes and corner. Distributed Multi-Scenario Analysis (DMSA) refers to timing analysis at different scenarios in a distributed manner.
How does Primetime mode merge and multi voltage aware analysis work?
Going beyond multi-scenario analysis, PrimeTime mode merging and simultaneous multi-voltage aware analysis (SMVA) actively work to reduce the number of scenarios to be analyzed. This allows users to reduce the hardware resources and turnaround time for multi-scenario analysis, while maintaining signoff quality timing correlation.
What are the different scenarios in DMSA Sta?
Scenarios are combination of various operating corners (process, voltage, temperature, RC corners) and different operating modes (functional mode, test mode, sleep mode, read mode, write mode etc). Scenarios can be different for timing and power analysis.